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K6T2008V2A, K6T2008U2A Family
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 1.0 2.0
History
Design target Finalize Revised - Add FBGA type package Errata correction - Removed TTL Compatible'from Features '
Draft Data
May 26, 1998 October 8, 1998 July 21, 1999
Remark
Advance Final Final
2.01
October 24, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology: TFT * Organization: 256Kx8 * Power Supply Voltage K6T2008V2A Family: 3.0V~3.6V K6T2008U2A Family: 2.7V~3.3V * Low Data Retention Voltage: 2V(Min) * Three State Outputs * Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F 48-FBGA-6.00x7.00
CMOS SRAM
GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by SAMSUNGs advanced CMOS process technology. The family support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery backup operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Max) 10A 30mA2) 15A Operating (ICC2,Max) PKG Type
K6T2008V2A-B K6T2008U2A-B K6T2008V2A-F K6T2008U2A-F
Commercial(0~70C)
3.0~3.6V 2.7~3.3V
70/85ns 70 /85/100ns 701)/85/100ns
1)
Industrial(-40~85C)
3.0~3.6V 2.7~3.3V
32-TSOP1-0820F 32-TSOP1-0813.4F 48-FBGA-6.00x7.00
1. The parameters are tested with 30pF test load 2. K6T2008V2A Family = 35mA
PIN DESCRIPTION
1 A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 2 3 4 5 6 A
A0 A1 CS2 A3 A6 A8
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
B
I/O5
A2
WE
A4
A7
I/O1
A16 A15
32-TSOP1 32-sTSOP1 Type - Forward
C
I/O6
NC
A5
I/O2
A14 A13
D
Vss
Vcc
A12 A11 A10
Row select
Memory array 1024 rows 256x8 columns
E
Vcc
Vss
F
I/O7
NC
A17
I/O3
A9 A8
G
I/O8
OE
CS1
A16
A15
I/O4
A7
H
A9
A10
A11
A12
A13
A14
I/O1
48-FBGA: Top View (Ball Down)
I/O8
Data cont
I/O Circuit Column select
Name
Function
Name
Function
Data cont
CS1,CS2 Chip Select Inputs OE WE A0~A17 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O8 Data Inputs/Outputs Vcc Vss NC Power Ground No Connection
CS1 CS2 WE OE A0 A1 A17 A6 A5 A4 A3 A2
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
PRODUCT LIST
Commercial Temperature Products(0~70C) Part Name K6T2008V2A-TB70 K6T2008V2A-TB85 K6T2008U2A-TB70 K6T2008U2A-TB85 K6T2008U2A-TB10 K6T2008V2A-YB70 K6T2008V2A-YB85 K6T2008U2A-YB70 K6T2008U2A-YB85 K6T2008U2A-YB10 Function 32-TSOP1-F, 70ns, 3.3V,LL 32-TSOP1-F, 85ns, 3.3V,LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.3V,LL 32-sTSOP1-F, 85ns, 3.3V,LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL
CMOS SRAM
Industrial Temperature Products(-40~85C) Part Name Function 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-TSOP1-F, 100ns, 3.3V, LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 100ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL 48-FBGA, 70ns, 3.3V, LL 48-FBGA, 85ns, 3.3V, LL 48-FBGA, 70ns, 3.0V, LL 48-FBGA, 85ns, 3.0V, LL
K6T2008V2A-TF70 K6T2008V2A-TF85 K6T2008V2A-TF10 K6T2008U2A-TF70 K6T2008U2A-TF85 K6T2008U2A-TF10 K6T2008V2A-YF70 K6T2008V2A-YF85 K6T2008V2A-YF10 K6T2008U2A-YF70 K6T2008U2A-YF85 K6T2008U2A-YF10 K6T2008V2A-FF70 K6T2008V2A-FF85 K6T2008U2A-FF70 K6T2008U2A-FF85
FUNCTIONAL DESCRIPTION
CS1 H X1) L L L CS2 X
1)
OE X
1)
WE X
1)
I/O High-Z High-Z High-Z Dout Din
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
L H H H
X1) H L X1)
X1) H H L
1. X means dont care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5 -0.3 to 4.6 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C Remark K6T2008V2A-B, K6T2008U2A-B K6T2008V2A-F, K6T2008U2A-F
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product K6T2008V2A Family K6T2008U2A Family All Family K6T2008V2A, K6T2008U2A Family K6T2008V2A, K6T2008U2A Family Min 3.0 2.7 0 2.2 -0.33)
CMOS SRAM
Typ 3.3 3.0 0 Max 3.6 3.3 0 Vcc+0.3 0.6 Unit V V V V
Note: 1. Commercial Product: TA=0 to 70C, otherwise specified Industrial Produc t: TA=-40 to 85C, otherwise specified 2. Overshoot: Vcc+2.0V in case of pulse width30ns 3. Undershoot: -2.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS)
1. K6T2008V2A Family = 35mA 2. Industrial product = 15A
Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
Min Typ Max Unit -1 -1 2.4 25 0.2 1 1 5 4 301) 0.4 0.3 102) A A mA mA mA V V mA A
VOL VOH ISB ISB1
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs = VIH or VIL CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V, Other inputs=0~Vcc
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS (K6T2008V2A Family: VCC=3.0~3.6V, K6T2008U2A Family: VCC=2.7~3.3V
Commercial Product: TA=0 to 70C, Industrial Product: TA=-40 to 85C) Speed Bins Parameter List Symbol 70ns Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 10 5 0 0 10 70 60 0 60 55 0 0 30 0 5 Max 70 70 35 25 25 25 Min 85 10 5 0 0 15 85 70 0 70 60 0 0 35 0 5 85ns Max 85 85 40 25 25 30 100ns Min 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 5 Max 100 100 50 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR CS1Vcc-0.2V1) Vcc=3.0V, CS1Vcc-0.2V
1)
Test Condition
Min 2.0 0 5
Typ 0.2 -
Max 3.6 10 2)
Unit V A ms
See data retention waveform
1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled) 2. Industrial Products = 15A
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
CMOS SRAM
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. tWR2 is applied in case a write ends with CS2 going low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 3.0/2.7V 1) tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC - 0.2V
CS1 GND
CS2 controlled
VCC 3.0/2.7V1) CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND
1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family
CS20.2V
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
CMOS SRAM
Units: millimeter(inch)
+0.10 -0.05 +0.004 0.008 -0.002
0.20
20.000.20 0.7870.008 #32 ( 8.00 0.315 0.25 ) 0.010
#1
8.40 0.331MAX
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047MAX
+0.10 -0.05 +0.004 0.006 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004 0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
0.20
+0.10 -0.05 0.008+0.004 -0.002
13.400.20 0.5280.008 #32 ( 8.00 0.315 0.25 ) 0.010
#1
8.40 0.331 MAX
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX 11.800.10 0.4650.004
+0.10 -0.05 0.006+0.004 -0.002
0.25 0.010 TYP
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
1.10 MAX 0.004 MAX
0.10 MAX 0.004MAX 0.05 0.002 MIN
Revision 2.01 October 2001
K6T2008V2A, K6T2008U2A Family
PACKAGE DIMENSIONS
48 BALL FINE PITCH BALL GRID ARRAY(6.00X7.00)
Top View Bottom View B B 6 A #A1 B C D 5 4 B1
CMOS SRAM
Units: millimeters
A1 INDEX MARK 0.50 0.50
3
2
1
C1 E C1/2 F G H B/2 Detail A A 0.25/Typ. Y 0.85/Typ. Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max)
Side View D
C
Min A B B1 C C1 D E E1 E2 Y 5.90 6.90 0.30 0.20 -
Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.10 0.85 0.25 -
Max 6.10 7.10 0.40 1.20 0.30 0.08
C
Revision 2.01 October 2001
C
0.30 E1 E
E2

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